This invention is applicable to the circuit of the clock generator inside IC chip. Specifically, the invention is primarily applicable to reduce and eliminate the mismatch effect in the delay units of the clock generator. On the other hand, this invention is also applicable to generate exacter and more phases in a clock period and output high-frequency clock signals at low-frequency operating clock.
Because the ring-type oscillators and the delay lines composed of delay units can output accurate phase delay, these circuits are widely used in the integrated circuit design. Their applications include: clock timing and synchronous circuit, time-to-digital converter, and timing recovery circuit.
In a few high-speed systems, output phases of all delay units will link to outer parts for controlling the procedure of data processing. Because with the increasing of the applied operating frequency, the period of data processing is getting shorter and shorter. Also, if the circuits of the delay units don""t match with outer environment and inner status, the timing margin of the clock signal will get much narrower to raise the complexity of the data processing terribly. Furthermore, with the ongoing advance of fabrication process, the problem of circuit mismatch will be getting worse and worse because of the circuit element""s shrinkage.
On the other hand, the minimum phase resolution of the clock generator composed of delay units is the delay time of one delay unit. So as far as a single-output system is concerned, the better phase resolution is achieved by the current-mode phase interpolation circuit. As for a multi-output system, the better resolution is achieved by the array of ring-type oscillators or the array of delay lines. In spite of more accurate phase resolution can be acquired in these ways, the overall circuit area, power consumption, and system complexity will totally get increasing.
In the invention, a clock generator is proposed. Specifically, the circuit of the proposed clock generator is added with a set of averaging amplifiers and averaging impedances, here is using resistors for example, for resolving the non-linearity problem of the mismatch effect of the delay units. And, the proposed clock generator uses voltage-mode phase interpolation circuit constructed of resistors to promote the phase resolution.
The invention proposes that if outputs of all delay units connect to inputs of all averaging amplifiers separately, the averaging amplifiers will act as buffers to make the delay units independent of variation of external loads. Generally, in order to reduce the non-linearity problem originated from the mismatch effect, the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers and all other averaging amplifiers proceed to connect mutually to form a whole closed loop. Because the load of the averaging amplifier is a pair of current sources, i.e. a load with infinite output impedance, most of signal currents will go into the averaging impedances. Moreover, if the resistance of the averaging impedances is much smaller than the impedance of the averaging amplifiers, the non-linearity phase problem will be resolved to achieve optimization.
On the other hand, in two adjacent averaging amplifiers, the invention proposes to apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more accurate phase interval. It is obtained by directly linking the lines out of the nodes of the averaging impedances.
In the invention, the characteristics and advantages of the circuit architecture will be further clarified in the following figures and illustrations for more detailed comprehension.